The objective of this thesis is to implement the two low transistor count full adders using submicron CMOS technologies and to study their performance with respect to process variations and single-transistor faults. One adder uses 10 transistors and the other uses 14 transistors. Hence they are respectively called the 10T and 14T adders. Previous work has studied the implementation of the static Complementary Metal Oxide Semiconductor (CMOS) adder, Complementary Pass Transistor Logic (CPL) adder, Transmission Gate adder (TGA) and the Hybrid CMOS (HCMOS) adder. The performance of the 10T and 14 T adders using the above mentioned metrics are compared with these adders and conclusions are made as to which adders are the best candidates for implementation in nanoscale technologies. The method for implementing the 10T and 14T full adders includes the analysis of the circuit schematic and the construction of its physical layout using the Electric layout design tool. The netlists are extracted with the assigned parasitic capacitances and are simulated to calculate the delays with different capacitive loads and the variations in the supply voltage. The power dissipation is calculated using a fan-out-of-four load. This same circuit configuration is also used to calculate the delays for a range of supply voltages.As deep submicron technologies are known to experience increasingly larger variations in process parameters, their impact on the performance of the CMOS, CPL, TGA, HCMOS, 10T and 14T full adders is studied. The Fast NMOS and Fast PMOS design corner, nominal and Slow NMOS and Slow PMOS design corner model files are generated for different technology nodes with the process variations using the Predictive Technology Model (PTM) website and the respective delays are calculated for all the adders. The adders are analyzed for fault detectability by using a stuck-open and stuck-short Metal Oxide Semiconductor Field Effect Transistor (MOSFET) fault model. After examining the effect of such faults on each MOSFET in the adders under study, they are ranked according to the ease with which a fault can be detected. The effect of fault analysis using the quiescent supply current (IDDQ) testing is also studied. Previously, these adders were studied at 180 nm node or above. The contribution of this thesis is the comprehensive analysis of the above mentioned adders for process variations and fault detectability in deep submicron processes. Specific results from this study include the following: the low transistor count adders (10T and 14T) do not scale well in terms of delay performance when implemented in nanoscale CMOS technologies. The main reason is the reduction in power supply voltage that is mandated in the deep submicron regime. This has a detrimental effect on the signal paths that use only a single transistor pass gate. This situation frequently occurs in adder circuits that attempt to minimize the transistor counts. As for fault detectability, previously there has been no comprehensive study of the adders in this regard. Some specific conclusions from this work include the following: it is found that the best adder circuits allow the memory states that occur when a transistor is stuck open to be effectively utilized. The singular paths of the 10T adder and the complementary logic networks of thestatic CMOS adder allowed them to be ranked highest for detectability. In terms of performance with respect to process variation and delay, the TGA adder and static CMOS adders performed best. In summary, this thesis provides some important guidelines for implementing adder circuits in nanoscale CMOS technologies. Specifically, circuits that ensure full voltage swings at all internal nodes by using full CMOS transmission gates (TGA) or complementary logic trees (static CMOS) are the best candidates for implementations in deep submicron processes.

Date of publication

Fall 11-2011

Document Type




Persistent identifier