Interest in cadmium sulfide (CdS) as a semiconductor for thin film transistors (TFTs) first began in 1962. It is known that TFTs of CdS are not only compatible with flexible substrate design, but also exhibit channel mobilities that will exceed those of organic TFTs. Past efforts in analyzing top-contact, bottom-gate accumulation-mode polycrystalline transistors have been obstructed due to various complications. One of the complications is due to dependence of threshold voltage on existing defect states in the semiconductor. The other two dependencies are on semiconductor thickness and on metal-semiconductor drain-source contact properties. The prediction of the accumulation-mode threshold voltage begins with baseline terms such as flat-band voltage and a voltage shift due to semiconductor-insulator interface charge. A refinement in the baseline approach is obtained by appending two voltage shifts. One due to defect states created by grain boundaries and other due to dependence on semiconductor thickness. The non-monotonic dependence on threshold voltage with semiconductor thickness has been attributed in part due to the source/drain contacts being Schottky barrier type. The proposed Semi Empirical Accumulation Mode Transistor model forCdS (SEAMM) is tested with measured data taken from a fabricated aluminum-contact polycrystalline CdS TFT. The semi-empirical approach combines analysis with both simulation data and experimental data. The SEAMM was then brought into alignment with results for a fabricated CdS transistor by adjusting the interface charge. Predictions from SEAMM produced transfer characteristic curves which were shown to be in good agreement with experimental data.
Date of publication
Thesis (Local Only Access)
Pasupuleti, Naga Surya, "Semi-Empirical Cadmium Sulfide Transistor Model Combining Grain Defects and Semiconductor Thickness Variation" (2014). Electrical Engineering Theses. Paper 24.